1. Field of the Invention
This invention relates to an apparatus and method for orienting semiconductor wafers and more particularly to orienting a plurality of such wafers so that the flat sides of the wafers lie in a common plane.
2. Description of the Prior Art
In manufacturing integrated circuits a boule of semiconductor material, such as silicon, is grown and thereafter the boule is cut into slices. The surfaces of the slices are polished to a high degree of flatness and then a chordally extending flat edge portion is formed on the periphery of each slice or wafer, the flat side typically bearing a predetermined relationship to a crystallographic axis of the material of which the wafer is formed. Throughout further processing of a wafer the flat edge portion is employed as a reference in order that the position and orientation of subsequence operations will be as desired.
It is typical to transport a plurality of wafers between various operating stations in a tray. A typical wafer tray include a pair of sidewalls that are supported in rigid spaced apart relation to one another. The sidewalls have a plurality of protruding ribs between each adjacent pair of which is formed a slot for receiving a single wafer. A typical wafer tray has 25 such slots and thus is capable of supporting 25 wafers. The typical tray has a truncated or open lower portion so that access can be had to the peripheral edges of the wafers. Processing the wafers usually requires removal of the wafers from the tray; processing is expedited and facilitated if the flat edge portions of all wafers in a tray are positioned in a common plane at or near either the top of the tray or the bottom of the tray.
A wafer tray of the type referred to above is shown in IBM Technical Disclosure Bulletin, vol. 10, No. 6, November 1967, page 828 in an article entitled "Semiconductor Wafer Alignment Fixture" by Delgado. The apparatus shown in such bulletin operates on wafers that have a semicircular cutout to orient all wafers with the semicircular cutout at the bottom of the wafer tray.
Other known prior art operates on wafers singly; such prior art is described in the following U.S. Pat. Nos. 3,297,134; 3,982,267; and 3,997,065.